1. Field of the Invention
This invention relates to the field of data processing. More particularly, this invention relates to digital adder circuits used within data processing systems.
2. Description of the Prior Art
Addition is one of the most important arithmetic operations that is frequently performed within data processing systems. A problem with producing high speed adder circuits is that the high order bits of the result are dependent upon the carry out values from the low order bits. The consequence of this is that addition operations tend to be relatively slow. It is a constant aim within data processing systems that they should operate as rapidly as possible and to this end considerable effort has been expended over many years in designing and developing adder circuits that are capable of operating at high speed.
In an effort to operate at higher speeds techniques have been proposed in which the carry bits for a sum of two input operands are calculated separately to an exclusive OR operation performed upon the two input operands with the results being combined at the final stage to produce the sum.
An example of such a technique is the Brent and Kung adder described in the paper "A regular layout for parallel adders", R P Brent and H T Kung, IEEE Trans. Comput, Volume 31, pages 260 to 264, March 1982.
Whilst such carry bit calculation schemes improve performance, the carry computation requires several layers of logic to perform. This logic consumes circuit area and power as well as limiting the ultimate performance that can be achieved.
It is an object of the invention to address the above mentioned problems.